Xiaochen Guo


I received my M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester in 2011 and 2015, respectively. I worked with my Ph.D. adviser Prof. Engin Ipek on leveraging resistive memories to build energy-efficient processors, memory systems, and accelerators. I am a two-time recipient of the IBM Ph.D. Fellowship. Before coming to the University of Rochester, I received my bachelor’s degree in Computer Science and Engineering from Beihang University in 2009.

About Me

Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek and Eby G. Friedman, “Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing,” in the IEEE Transactions on Very Large Scale Integration Systems (TVLSI).

Isaac Richter, Kamil Pas, Xiaochen Guo, Ravi Patel, Ji Liu, Engin Ipek, and Eby G. Friedman, “Memristive Accelerator for Extreme Scale Linear Solvers,” the Government Microcircuit Applications & Critical Technology Conference (GOMAC), St. Louis, MO, March 2015.

Qing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek and Eby G. Friedman, “AC-DIMM: Associative Computing with STT-MRAM,” in Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.

Qing Guo, Xiaochen Guo, Yuxin Bai, and Engin Ipek, “A Resistive TCAM Accelerator for Data Intensive Computing,” in Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011.

Xiaochen Guo, Engin Ipek and Tolga Soyata, “Resistive Computation: Avoiding the Power Wall with Low-Leakage, STT-MRAM Based Computing,” in Proceedings of the 37th International Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 2010.

Bo Xiao, Liandong Liu, Xiaochen Guo, and Ke Xu, “Modeling the IPv6 Internet AS-level Topology,” Physica A, 388(2009): 529-540. doi: 10.1016/j.physa.2008.10.034.

Fully Refereed Archival Publications

Book Chapters

Engin Ipek, Qing Guo, Xiaochen Guo, and Yuxin Bai, “Resistive Memories in Associative Computing,” in Emerging Memory Technologies: Design, Architecture, and Applications, Yuan Xie (Editor), Springer, July 2013.


Xiaochen Guo and Arun Jagatheesan, “Page Merging for Buffer Efficiency in Hybrid Memory Systems,” U.S. Patent 8,874,827, October 28, 2014.

Teaching Assistantships

2011 Spring - Computer Organization (ECE 200), University of Rochester

2010 Fall      - Computer Architecture (ECE 401), University of Rochester

2009 Spring - Introduction to Computer Science, Beihang University


2011 Summer - Research Intern at Samsung Information Systems America, Inc.

2012 Summer - Research Intern at IBM T. J. Watson Research Center

2013 Summer - Research Intern at IBM T. J. Watson Research Center

Assistant Professor

Department of Electrical and Computer Engineering

Lehigh University

Email: xig515 AT lehigh DOT edu

I joined the ECE department at Lehigh University as a tenure-track assistant professor in August, 2015. My webpage has been moved to www.lehigh.edu/~xig515

I am looking for highly motivated students who are interested in computer architectures to join my research group at Lehigh.