Summary of Recent Research Topics

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering
Department of Electrical and Computer Engineering
University of Rochester
Rochester, New York 14627

High Performance Digital and Analog Integrated Circuit Design
The focus of this research is the design and analysis of high performance digital and analog integrated circuits, and supporting design techniques, methodologies, CAD tools, and circuit structures. Speed, area, power dissipation, and reliability tradeoffs in CMOS technology are investigated in terms of application-specific constraints and fundamental circuit level limitations. The general approach is to apply analog signal concepts to the design and analysis of high complexity integrated systems to maximize both circuit and system level performance while satisfying the complexity requirements inherent to the VLSI complexity environment.

Three-Dimensional Integrated Design Methodologies, Algorithms, and Test Circuits
Three-dimensional (3-D) integration has become an important platform for building complex, heterogeneous integrated systems. Systems composed of a variety of functions and technologies require integration into a single form factor. These systems often require high performance microprocessors, high density memory, video/image processing, MEMS, temperature sensing, photonics – based a on a variety of exotic technologies such as nanometer CMOS, GaAs, InP, HgCdTe, waveguides, and much more. 3-D is a natural platform to support these multi-faceted systems. Algorithms and design techniques focusing on TSV-based 3-D integration are under development. These capabilities are being demonstrated on a variety of 3-D test circuits.

Circuits, Models, and Architectures Based on Emerging Technologies
With the end of classical CMOS scaling approaching, a number of exotic technologies are under development to continue the semiconductor revolution. The focus of this research is on developing innovative models, circuits, architectures, and design methodologies and algorithms that exploit the unusual capabilities of these niche technologies. Some examples of these exciting new technologies are STT-MRAM, RRAM, magnetic tunnel junctions, photonic ICs, memristors, nanowires, graphene, and superconductive SFQ. This research area requires a merging of a materials/device background with practical circuit and architecture design when building extremely high performance (i.e., high speed, low power, mixed-signals, low noise) systems.

Efficient Power Delivery for Highly Complex Integrated Systems
The effective operation of high complexity heterogeneous integrated circuits strongly depends upon the quality of the power delivered to the system; specifically, voltage conversion and regulation, power distribution, and power management. A comprehensive approach is under development for the simultaneous design of locally distributed, adaptive ultra-small on-chip point-of-load voltage regulators, decoupling capacitors, and localized power controllers. The multiple interactions among tens to hundreds of on-chip point-of-load voltage regulators, many tens to hundreds of thousands of decoupling capacitors, several billion loads, and multiple power networks are under focused investigation. Small and fast voltage regulators, on-chip decoupling capacitor placement strategies, locally intelligent power controllers, and mesh-based power network analysis algorithms for both 2-D and 3-D systems are examples of current topics of research.

On-Chip Interconnect, Power, and Substrate Coupling Noise
Interconnect, power, and substrate noise are issues of primary concern in high speed digital and mixed-signal integrated circuits. The focus of these research efforts is on interpreting, designing, and compensating for the effects of RLC interconnect, power network, and substrate impedances. Particular emphasis is placed on the on-chip global signals, such as the clock and power distribution networks and the interactions of these networks with the substrate, neighboring interconnect, and the on-chip decoupling capacitors.

High Performance Clock Distribution Networks
Most high complexity integrated systems utilize fully synchronous timing, requiring a globally distributed clock signal as a temporal reference signal to control the sequence of operations. This high speed clock signal is distributed to every register to arrive at a precise time. The focus of this research is the automated synthesis of high speed, highly reliable clock distribution networks. Clock tree synthesis (CTS) algorithms are under development to support non-zero clock skew scheduling for both nanometer CMOS and emerging technologies. This capability is being developed as an integrated synthesis system, validated with benchmark circuits, and tested with manufactured demonstration circuits.

Integrated Pipelining, Retiming, and Clock Scheduling
For the optimal behavioral synthesis of a synchronous system, the processes of pipelining, retiming, and clock skew scheduling must be implemented in an integrated fashion. Physically accurate algorithms are being developed to more efficiently synthesize these high performance synchronous systems. These results will provide a systematic procedure for building high performance recursively structured pipelined systems and related clock distribution networks.