WCED Final Program

Sunday, June 20, 2004
8:00-9:00AM Keynote Presentation
  • "Complexity-Effective Processors in the Nanotechnology Era," Antonio Gonzalez (UPC and Intel)


    •  9:00-10:00AM Register Files and Caches
  • "Scalable Distributed Register File," R. Gonzalez, A. Cristal, M. Pericas, A. Veidenbaum, and M. Valero (UPC and University of California, Irvine)


  • "Cache Pipelining with Partial Operand Knowledge," E. Gunadi and M. Lipasti (University of Wisconsin-Madison)


    •  10:00-10:30AM Break

    10:30AM-12:00PM Multi-Threading
  • "Approaching a Smart Sharing of Resources in SMT Processors," F.J. Cazorla, E. Fernandez, A. Ramirez, and M. Valero (UPC and University of Las Palmas de Gran Canaria)


  • "AP+SOMT: Agent-Programming Combined with Self-Organized Multi-Threading," Y. Lhuillier and O. Temam (Paris South University and INRIA)


  • "Threads on the Cheap: Multithreaded Execution in a WaveCache Processor," S. Swanson, A. Schwerin, A. Petersen, M. Oskin, and S. Eggers (University of Washington)


    •  12:00-1:30PM Lunch

    1:30-3:00PM Power and Temperature-Aware Microarchitecture
  • "Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors," K. Ramani, N. Muralimanohar, and R. Balasubramonian (University of Utah)


  • "Temperature-Aware Design Issues for SMT and CMP Architectures," J. Donald and M. Martonosi (Princeton University)


  • "Design Choices for Thermal Control in Dual-Core Processors," S. Ghiasi and D. Grunwald (University of Colorado at Boulder)


    •  3:00-3:30PM Break

    3:30-5:30PM Processor Microarchitecture and Performance Monitoring
  • "Refining Performance Monitor Design," H.C. Hunter and R. Nair (University of Illinois at Urbana-Champaign and IBM)


  • "A Complexity-Effective Decoding Architecture Based on Instruction Streams," O.J. Santana, A. Falcon, A. Ramirez, and M. Valero (UPC)


  • "An Ahead Pipelined Alloyed Perceptron with Single Cycle Access Time," D. Tarjan, K. Skadron, and M. Stan (University of Virginia)


  • "Multicycle Broadcast Bypass: Too Readily Overlooked," P.G. Sassone and D.S. Wills (Georgia Institute of Technology)


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