Workshop on Complexity-Effective Design
June 20, 2004
To be held in conjunction with the 31st International Symposium on Computer
Architecture (ISCA 31)
David H. Albonesi
University of Rochester
IBM T. J. Watson Research Center
The quest for higher performance via deep pipelining (for high clock
rate) and speculative, out-of-order execution (for high IPC) has yielded
processors with greater performance, but at the expense of much greater
design complexity. The costs of higher complexity are many-fold, including
increased verification time, higher power dissipation, and reduced scalability
with microarchitectural resource size parameters and process shrinks. The
goal of this workshop is to provide a forum for microarchitects, circuit
designers, performance modelers, compiler developers, verification experts,
and system designers to discuss and explore hardware/software techniques
and tools for creating future designs that are more complexity-effective
For the purposes of this workshop, a CE design feature or tool either
(a) yields a significant performance and/or power efficiency improvement
relative to the increase in hardware/software complexity incurred; or (b)
significantly reduces complexity (design time and/or verification time
and/or improved scalability and/or power consumption) with a tolerable
performance impact. Please refer to the review
article by the workshop organizers for a detailed discussion of CE design.
In presenting this workshop for the fifth time,
we hope to focus it more on the following topics:
Metrics for establishing the CE of a given design. Scalability criteria
and evaluation. Quantifying verification complexity. Power-performance
Characterization of current and emerging workloads to help determine the
CE value of alternate design paradigms.
The merits of different architectural approaches (ooo versus in-order superscalar,
VLIW/EPIC, clustered microarchitectures, chip multiprocessor, multithreading,
multi-clock, GALS, and asynchronous architectures,
etc.) in terms of their CE.
Comparison of these approaches in terms of CE using new or established
Case studies of actual designs in which CE was taken into account.
Pipeline depth and CE issues, including "helper" pipeline approaches.
Analytical models for power-performance or performance-verifiability tradeoffs.
Impact of clock- and Vdd-gating
on verification and reliability in power-aware designs.
Approaches to improving power-efficiency without unduly increasing design
Microarchitectures that scale effectively with process shrinks/variations.
Complexity-effective cache and memory hierarchy design.
Compiler and operating system support for CE, e.g., moving functionality
to software in order to reduce overall design complexity.
Full conference length papers are fine but not a requirement. Short
idea/position papers addressing one of the above issues are
Dave Albonesi, University of Rochester
Iris Bahar, Brown University
Pradip Bose, IBM Watson
Alper Buyuktosunoglu, IBM Watson
George Cai, Intel
Babak Falsafi, CMU
Keith Farkas, Hewlett Packard
Antonio Gonzalez, UPC and Intel
Diana Marculescu, CMU
Gokhan Memik, Northwestern University
Chuck Moore, AMD
Subbarao Palacharla, McDATA Corporation
Submission deadline (extended abstract or full paper in PDF format emailed
to any of the co-chairs): May 10, 2004 (extended)
Acceptance notification: May 17, 2004
Final version due: May 24, 2004
A post-workshop proceedings, containing abstracts, full papers, and/or
talk slides, will be distributed.