WCED Final Program

9:00-9:45 Invited Presentation
  • Smart and Cool -- The Search for Power-Effective Design, Ronny Ronen and Guillermo (Eli) Savransky (Intel Israel/MRL)


    •  9:45-10:15 Break

     10:15-12:00 Power-Aware Computing

  • Way Memoization to Reduce Fetch Energy in Instruction Caches, A. Ma, M. Zhang, and K. Asanovic (MIT)


  • Evaluating Design Tradeoffs in Dual Speed Pipelines, R. Pyreddy and G. Tyson (University of Michigan)


  • Reducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage Supply, V. Moshnyaga (Fukuoka University)


  • Dynamic Allocation of Datapath Resources for Low Power, D. Ponomarev, G. Kucuk, and K. Ghose (State University of New York, Binghamton)


    •  12:00-1:30 Lunch

    1:30-2:00 Invited Paper
  • Managing Complexity in the Piranha Server-Class Processor Design, Luiz Andre Barroso, Kourosh Gharachorloo, Mosur Ravishankar, and Robert Stets (Compaq Western Research Laboratory)


    •  2:00-3:15 Models and Tools

  • Transistor Count and Chip-Space Estimation of SimpleScalar-based Microprocessor Models, M. Steinhaus (University of Karlsruhe), R. Kolla (University of Wurzburg), J. Larriba-Pey (UPC), Theo Ungerer (University of Augsburg), and M. Valero (UPC)


  • Theoretical System-Level Model for Power-Performance Trade-Off in VLSI Microprocessor Design, M. Olivieri (La Sapienza University of Rome)


  • Live, Runtime Power Measurements as a Foundation for Evaluating Power/Performance Tradeoffs, R. Joseph, D. Brooks, and M. Martonosi (Princeton University)


    •  3:15-3:45 Break

    3:45-5:30 Processor Design
  • Complexity-effective Enhancements to a RISC CPU Architecture, J. Scott, J. Arends, and B. Moyer (Motorola)


  • Saving and Restoring Implementation Contexts with co-Designed Virtual Machines, D. Dhodapkar and J. Smith (University of Wisconsin-Madison)


  • Revisiting Direct Tag Search Algorithm On Superscalar Processors, T. Sato (Kyushu Institute of Technology), Y. Nakamura (NEC Telecom Systems), and I. Arita (Kyushu Institute of Technology)


  • The Span Cache: Software Controlled Tag Checks and Cache Line Size, E. Witchel and K. Asanovic (MIT)


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