Workshop on Complexity-Effective Design

June 30, 2001
Goteborg, Sweden

To be held in conjunction with the 28th International Symposium on Computer Architecture (ISCA 28)

Final Program


David H. Albonesi
University of Rochester

Pradip Bose
IBM T. J. Watson Research Center

Subbarao Palacharla
Sanera Systems


The quest for higher performance via deep pipelining (for high clock rate) and speculative, out-of-order execution (for high IPC) has yielded processors with greater performance, but at the expense of much greater design complexity. The costs of higher complexity are many-fold, including increased verification time, higher power dissipation, and reduced scalability with process shrinks/variations. The goal of this workshop is to provide a forum for microarchitects, circuit designers, performance modelers, compiler developers, verification experts, and system designers to discuss and explore hardware/software techniques and tools for creating future designs that are more complexity-effective (CE).

For the purposes of this workshop, a CE design feature or tool either (a) yields a significant performance and/or power efficiency improvement relative to the increase in hardware/software complexity incurred; or (b) significantly reduces complexity (design time and/or verification time and/or improved scalability) with a tolerable performance and/or power impact. In presenting this workshop for the second time, we hope to focus it more on the following topics:

Program Committee:


Submission deadline (10 pages maximum in postscript or PDF format emailed to any of the co-chairs): May 4, 2001
Acceptance notification: May 18, 2001
Final version due: June 1, 2001

Workshop proceedings will be distributed.