Workshop on Complexity-Effective Design
June 30, 2001
To be held in conjunction with the 28th International Symposium on Computer Architecture (ISCA 28)
David H. Albonesi
University of Rochester
IBM T. J. Watson Research Center
The quest for higher performance via deep pipelining (for high clock
rate) and speculative, out-of-order execution (for high IPC) has
yielded processors with greater performance, but at the expense of
much greater design complexity. The costs of higher complexity are
many-fold, including increased verification time, higher power
dissipation, and reduced scalability with process shrinks/variations.
The goal of this workshop is to provide a forum for microarchitects,
circuit designers, performance modelers, compiler developers,
verification experts, and system designers to discuss and explore
hardware/software techniques and tools for creating future designs
that are more complexity-effective (CE).
For the purposes of this workshop, a CE design feature or tool either
(a) yields a significant performance and/or power efficiency
improvement relative to the increase in hardware/software complexity
incurred; or (b) significantly reduces complexity (design time and/or
verification time and/or improved scalability) with a tolerable
performance and/or power impact.
In presenting this workshop for the second time, we hope to focus it
more on the following topics:
- Metrics for establishing the CE of a given design. Scalability
criteria and evaluation.
- Characterization of current and emerging workloads to help determine
the CE value of alternate design paradigms.
- The merits of different architectural approaches (ooo or in-order
superscalar, VLIW/EPIC, clustered microarchitectures, chip
multiprocessor, multithreading, etc.) in terms of their CE.
- Comparison of these approaches in terms of CE using new or
- Case studies of actual designs in which CE was taken into account.
- Pipeline depth and CE issues, including "helper" pipeline approaches.
- Analytical models for power-performance or performance-verifiability
- Design-for-verification architectures.
- Approaches to improving power-efficiency without unduly increasing
- Microarchitectures that scale effectively with process
- Complexity-effective cache and memory hierarchy design.
- Compiler and operating system support for CE, e.g., moving functionality
to software in order to reduce overall design complexity.
- Dave Albonesi, University of Rochester
- Todd Austin, University of Michigan
- Iris Bahar, Brown University
- Pradip Bose, IBM Watson
- George Cai, Intel
- Babak Falsafi, CMU
- Keith Farkas, Compaq
- Antonio Gonzalez, UPC
- Peter Hofstee, IBM
- Bill Mangione-Smith, UCLA
- Margaret Martonosi, Princeton University
- Subbarao Palacharla, Sanera Systems
- Jim Smith, University of Wisconsin
Submission deadline (10 pages maximum in postscript or
PDF format emailed to any of the co-chairs): May 4, 2001
Acceptance notification: May 18, 2001
Final version due: June 1, 2001
Workshop proceedings will be distributed.