Professor
Ph.D., University of Illinois, 2002
Dept. of Elec. & Comp. Eng.
University of Rochester
414 Computer Studies Building,
160 Trustee Rd.
P.O. Box 270231
Rochester, NY 14627-0231
Voice: 585-275-2111
Fax: 585-275-2073
Increasing reliance on computing as a means of scientific exploration demands ever higher speed, reliability, and efficiency from high-performance systems. Achieving sustained gain in all these metrics requires continued innovation in processor microarchitecture, the communication and coherency substrate, and the underlying device technology. Such innovation builds upon concrete understanding of the interaction of these components. Our research spans these components and focuses on delivering practical, complexity-effective solutions. In addition to architectural exploration, we are also investigating how to leverage new technologies and circuit techniques. For example, we are investigating the use of on-chip optics, spin-based devices, and high-speed communication circuitry. At the same time, architecture design is also driven by the demand of software. We are also interested in deepening the understanding of the behavior of real-world applications. For example, we are working with physicists who use computational means to study inertial confinement fusion.
Michael Huang received the BS degree in computer science and engineering from Tsinghua University, Beijing, in 1994, the MS and the PhD degree in computer science from University of Illinois at Urbana-Champaign in 1999 and 2002, respectively. From 1994 to 1997, he was a lead architect in building a 32-processor hierarchical shared-memory multiprocessor research prototype. He joined the faculty of the Electrical and Computer Engineering department in 2002. He spent 2010 on sabbatical at IBM T. J. Watson Research Center working on future POWER processor concept development.
His research interests include various aspects of high-performance computer architecture such as processor microarchitecture, communication and memory substrate, reliability, and energy-efficient and complexity-effective design. His is particularly interested in addressing emerging issues and exploring new capabilities in the underlying device, circuit, and manufacturing technology. He is a recipient of the NSF CAREER award and an IBM Faculty Award, and a member of the IEEE and the ACM.
ASPLOS’19
“Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance”, S. Kondguli and M. Huang,in Proc. of the 24th Int’l Conf. on Architectural Support for Programming Languages and Operating Systems, April 2019
ISCA’18
“Division of Labor: A More Effective Approach to Prefetching”, S. Kondguli and M. Huang,in Proc. of the 45th Int’l Symp. on Computer Architecture, June 2018
ISCA’11
“A Case for Globally Shared-Medium On-Chip Interconnect”, A. Carpenter, J. Hu, J. Xu, M. Huang, and H. Wu, in Proc. of the 38th Int’l Symp. on Computer Architecture, June 2011
ISCA’10
“An Intra-Chip Free-Space Optical Interconnect”, J. Xue et al., Proc. of the 37th Int’l Symp. on Computer Architecture, June 2010 
