
DividebyOddNumber InjectionLocked Frequency Dividers
 
Highspeed frequency dividers (a.k.a prescalers) are essential building blocks in wireless and wireline communications for functions such as frequency synthesis, quadrature signal generation, and multiplexing (MUX/DEMUX). For example, a prescaler is one of the major components in a phaselocked loop (PLL) (see Fig.1), which is widely used as frequency synthesizers in a radio transceiver. Currently, static or dynamic digital dividers are commonly used in RF/microwave PLLs [1]. They have simple structures, large bandwidth, and good robustness over process variations [2]. As the radio operation frequencies increase beyond the low GHz range, however, power consumption of digital dividers becomes a problem. It becomes increasingly difficult for them to meet a reasonable power budget. This is especially challenging in lowpower mobile applications. Furthermore, due to large power dissipation, highspeed digital dividers can also introduce considerable noise degradation. Therefore, a frequency divider with better power efficiency is urgently needed.  
Fig.1 Prescalar in a typical chargepump PLL [1].  
Injection locking is a special type of forced oscillation in nonlinear oscillators. Suppose a signal of frequency &omega_{i} is injected into an oscillator, which has a selfoscillation (freerunning) frequency &omega_{0}. When &omega_{i} is quite different from &omega_{0}, "beats" of the two frequencies are observed. As &omega_{i} approaches &omega_{0}, the beat frequency (&omega_{i}&omega_{0}) decreases. When &omega_{i} enters some frequency range very close to &omega_{0}, the beats suddenly disappear, and the oscillator starts to oscillate at &omega_{i} instead of &omega_{0}. Fig.2 shows this nonlinear behavior. The frequency range in which injection locking happens is called the locking range. Injection locking also happens when &omega_{i} is close to the harmonic or subharmonic of &omega_{0}, i.e., n&omega_{0} or 1/n&omega_{0}. They are called harmonic (or superharmonic) and subharmonic injection locking, respectively.  
Fig.2 Injection locking.  
A harmonicinjectionlocked oscillator can be used as a frequency divider, namely, an InjectionLocked Frequency Divider (ILFD)[3,4,5,6]. An ILFD has inherent advantage in both speed and power dissipation compared to a digital divider. It is fundamentally an oscillator at the subharmonic frequency of the input signal, which effectively lowers the speed requirement for the process technology by nfold. As a resonant circuit, only a fraction of the stored energy is dissipated in every cycle, which is determined by the quality factor Q of the resonator. This means that an ILFD can have significantly lower power consumption than a digital divider. The disadvantages of ILFDs are the limited locking range and division ratios. While the locking range enhancement technique is proposed in [4], This work of DividebyOdd ILFD is aiming at solving the problem of division ratios.  
Divideby2 ILFDAs shown in Fig.3, a differential LC oscillator has become a popular choice for ILFDs[4]. When there is no input signal, i.e., the oscillator is freerunning, there exists a signal at node A (the drain of the tail transistor, M_{tail}), which is at the second harmonic of the freerunning oscillation frequency f_{0}. Therefore, this topology is inherently suitable for divideby2 operation. On the other hand, it can only support frequency division ratio of even numbers (2, 4, 6 ...) due to the differential nature. This would limit its usage in applications where oddnumber division ratio (e.g., divideby3) is more desirable.
Fig.3 Divideby2 ILFD. Such a differential LC ILFD can be viewed as a special regenerative divider[7] in which the M_{1}, M_{2}, and M_{tail} act as a singlebalanced mixer, and the LC tank as the filter, with the feedback loop formed by the cross coupling (Fig.4). Frequency division happens when the 2ndharmonic current is injected into node A by M_{tail}, and switched by the differential pair of M_{1} and M_{2} to generate the mixing products. Then all other harmonics except the fundamental frequency component are filtered out. Because the nonlinearity of the switching operation of the differential pair M_{1} and M_{2} has odd symmetry, it can only generate mixing products of oddnumber orders, which corresponds to division ratios of even numbers (2, 4, 6 ...). In order to support dividebyoddnumber operation, it is necessary to find a new topology for the builtin "mixer".
Fig.4 Mixer Model for Divideby2 ILFD. DividebyOddNumber ILFDTo address this problem and maintain the differential topology, we construct a differential cascode topology by adding another differential pair of M_{3} and M_{4} (Fig.5). M_{3} and M_{4} convert the differential injection signal V_{inj} into differential currents, which mixes with M_{1} and M_{2}. Note M_{1} and M_{2} are no longer a differential pair because their source terminals are separated. Now the evenorder nonlinearity of M_{1} (similarly M_{2}) can generate the desired mixing product that corresponds to a division ratio of any odd number, e.g., 3.
Fig.5 Differential Cascode Topology for DividebyOdd ILFD. A shuntpeaking inductor L_{0} can be inserted between the source terminal of M_{1} and M_{2} as shown in Fig.6. L_{0} resonates with the parasitic capacitances at the injection signal frequency ((2n+1)f_{0}), and thus increases the signal amplitude injected into M_{3} and M_{4}. It also provides a shortcircuit current path at the fundamental frequency (f_{0}). Therefore, the upper half circuit (M_{1}, M_{2}, L_{0} and resonator) works as a differential LC oscillator at the fundamental frequency. Overall, we confine signals at different harmonics locally by circuit topology and filtering.
Fig.6 Differential Cascode Topology with ShuntPeaking Inductor for DividebyOdd ILFD. The differential input can be directly connected when the ILFD is integrated with an onchip differential source like a differential VCO. When a singleended source is used, a balun T_{1} is used to convert the singleended input signal to differential signals (Fig.7). T_{1} also helps to match the input impedance of M_{3} and M_{4} to the source impedance.
Fig.7 DividebyOdd ILFD with Input Balun. A prototype divideby3 ILFD was designed using the new topology with input frequency from 16GHz to 18GHz (Fig.8)[8]. It uses an onchip LC tank as the resonator. Note that other types of resonators can also be used in the implementations of the disclosed inventions. The prototype has been fabricated using a commercial 0.18um CMOS technology with lowresistivity epi silicon substrate and the die photo is shown in Fig.9 . The output signal spectrum in locked condition is shown in Fig.10. The 2nd and 3rd harmonics are 23dB and 21dB below the fundamental frequency, and a large part of them is contributed by the opendrain buffer at the output (singleended measurement). The locking range increases from 0.3GHz at injection power of 14dBm to 1GHz at 4dBm with little change in the center frequency as shown in Fig.11. The corresponding input port voltage is calculated using S11 and shown in Fig.12. Note that this is the singleended voltage (amplitude) at the primary of the balun with 1:1 transformation ratio. The ILFD can also be tuned by the varactors C_{t1} and C_{t2} with the freerunning frequency from 5.37GHz to 6.1GHz and the extended working range for the ILFD is shown in Fig.13. Fig.14 shows the phase noise performance of the ILFD at different injection power levels. The phase noise of the freerunning ILFD (no injection) and the signal source is also shown for comparison. Due to the low Q of inductors, the freerunning phase noise is not good at all. When the ILFD is in locked condition, the phase noise follows that of the signal source with a 910dB reduction at large injection power (3dBm and 3.7dBm) which matches well with the theoretical value 9.5dB. For small injection power (8dBm), the phase noise degrades only at large offset frequency.  
Fig.8 Divideby3 ILFD Prototype.  
Fig.9 Measured Spectrum of the Divideby3 ILFD Prototype. Fig.10 Measured Locking Range vs. Injeced Power for Divideby3 ILFD Prototype. Fig.11 Measured Locking Range vs. Port Voltage for Divideby3 ILFD Prototype. Fig.12 Extended Locking Range of the Divideby3 ILFD Prototype. Fig.13 Measured Phase Noise for Divideby3 ILFD Prototype. References[1]B. Razavi, Monolithic PhaseLocked Loops and Clock Recovery Circuits,IEEE Press, 1996. [2] B. Razavi, K.F. Lee, RanHong Yan, "A 13.4GHz CMOS Frequency Divider" Digest of Technical Papers IEEE SolidState Circuits Conference, 1618 Feb. 1994 Page(s):176  177 [3] R. Adler, "A Study of Locking Phenomena in Oscillators" Proc. IRE, vol.34, pp. 351357, June 1946 [4]H. Rategh and T. H. Lee, "Superharmonic InjectionLocked Frequency Dividers," IEEE J. SolidState Circuits, vol. 34, pp 813821, June, 1999. [5]H. Wu and A. Hajimiri, "A 19GHz, 0.5mW, 0.35um CMOS Frequency Divider with ShuntPeaking LockingRange Enhancement," IEEE ISSCC Dig. Tech. Papers, pp.412413, Feb., 2001. [6]B. Razavi, "A Study of Injection Locking and Pulling in Oscillators," IEEE J. SolidState Circuits, 39(9):14151424, Sept. 2004. [7]S. Verma, H. R. Rategh and T. H. Lee, "A Unified Model for InjectionLocked Frequency Dividers," IEEE J. SolidState Circuits, vol. 38, pp10151027, June, 2003. [8]H. Wu and L. Zhang, "A 16to18GHz 0.18¦Ìm EpiCMOS Divideby3 InjectionLocked Frequency Divider" Digest of Technical Papers IEEE SolidState Circuits Conference, 59 Feb. 2006 Page(s):602  603 
